RTL Power Optimization – New College Grad 2026 at NVIDIA

Ideal for a Master’s or PhD graduate in Electrical or Computer Engineering, this role targets those with hands-on experience in VLSI design, AI, and digital power optimization. You should have a solid foundation in low-power architecture and RTL-level design patterns. **What makes it worth a look...** NVIDIA offers a base salary between $116,000 and $218,500 for this on-site role in Santa Clara, California. Beyond the competitive pay, you will gain hands-on access to next-generation GPU and networking chip development while qualifying for equity and comprehensive benefits. **You might be a good fit if you...** * Have strong Python programming skills for building automation and AI-driven data pipelines. * Possess deep knowledge of Verilog and RTL-level power reduction techniques like clock gating. * Are experienced with power analysis tools such as PowerArtist or PrimeTime PX. * Understand backend flows including logic synthesis, placement, and routing.