Senior ASIC Timing Engineer at NVIDIA

Ideal candidates for this senior role have a BS or MS in Electrical or Computer Engineering, coupled with at least two to eight years of direct experience in static timing analysis. You are an expert in managing timing constraints and driving convergence for complex chip architectures. **What makes it worth a look...** NVIDIA offers a base salary range of $168,000 to $310,500 based on level and location, with roles available on-site in Santa Clara, Austin, Hillsboro, or Durham. You will be working on core GPU and SoC technology while receiving comprehensive equity and benefits packages. **You might be a good fit if you...** * Have hands-on experience with full-chip Static Timing Analysis (STA). * Can analyze and fix timing paths using ECOs, including crosstalk and noise. * Possess deep knowledge of physical design optimizations like routing and logic restructuring. * Understand timing closure in deep sub-micron process nodes.