Senior Dataflow Development Engineer - LPU at NVIDIA

You're a senior-level engineer with over 12 years of experience, ideally holding a BS or higher in CS/EE/CE, with a strong background in FPGA development, hardw

Work type: hybrid

Location: US, CA, Santa Clara | US, CA, Remote

Salary: $196,000 – $368,000/yr

Type: Full-time

You're a senior-level engineer with over 12 years of experience, ideally holding a BS or higher in CS/EE/CE, with a strong background in FPGA development, hardware dataflow, or hardware/software co-design. **What makes it worth a look...** This full-time hybrid role at NVIDIA offers a base salary range of $196,000 to $310,500 for Level 5 and $232,000 to $368,000 for Level 6, with equity and a comprehensive benefits package. **You might be a good fit if you...** * Have hands-on experience with RTL/HDL (Verilog, VHDL) or high-level synthesis (HLS) for building and debugging dataflow pipelines in hardware. * Possess strong C/C++ programming skills for host drivers, runtimes, or tooling, and are familiar with hardware interfaces like PCIe, DMA, and memory-mapped I/O. * Understand dataflow and streaming concepts such as pipelining, backpressure, buffering, and resource/area trade-offs.

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