Senior Dataflow Development Engineer - LPU at NVIDIA

You're a senior engineer with at least 12 years of experience in FPGA development, hardware dataflow, or hardware/software co-design, holding a BS or equivalent in CS/EE/CE. **What makes it worth a look...** NVIDIA is offering a hybrid role in Santa Clara, CA or remote, with a base salary range of $196,000-$310,500 for Level 5 and $232,000-$368,000 for Level 6, plus equity. **You might be a good fit if you...** * Have hands-on experience with RTL/HDL (Verilog, VHDL) or high-level synthesis (HLS) for building and debugging dataflow pipelines in hardware. * Possess strong C/C++ programming skills for host drivers, runtimes, or tooling, and are familiar with hardware interfaces like PCIe, DMA, or memory-mapped I/O. * Understand dataflow and streaming concepts such as pipelining, backpressure, buffering, and resource/area trade-offs.