Senior STA Engineer, Sub-chip at NVIDIA

You're a seasoned Physical Design Engineer with at least five years of hands-on Static Timing Analysis (STA) experience, holding a B.SC. or M.SC. in Electrical Engineering. **What makes it worth a look...** This full-time, on-site role at NVIDIA, a leader in high-speed communication devices, offers a chance to contribute to groundbreaking chip design. Based in Israel (Yokneam, Beer Sheva, or Tel Aviv), the company is known for its innovative technology and professional environment. **You might be a good fit if you...** * Perform advanced STA using Prime Time for HSIO at chiplet and FC levels. * Generate SDC and timing eco, debug timing paths, and understand constraints. * Have experience with signoff methodologies and AI for timing optimization. * Possess AI tools orientation or a desire to learn rapidly.